University of Tehran

School of Electrical and Computer Engineering

The Dependable Systems Design (DSD) group conducts research into the design and verification of low power, fault-tolerant and reliable VLSI systems, with particular emphasis on asynchronous circuit techniques and formal methods to achieve its goals.

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Welcome to DSD lab

Asynchronous design principles will play an increasingly important role in constructing future systems on a chip, implemented in semiconductor technologies beyond 65 nanometers. These principles can be directly used in the design of energy-efficient networks-on-chip and in chip communications in such systems. Asynchronous design approach can also be used in cryptography systems, which must be secure and reliable. Indeed, the lack of global clock encourages the use of such approach, where, thanks to unconventional encodings, it will be practically impossible to analyze the energy spectrum of cryptographic systems to find the key.

Verification of a digital design is one of the key factors to the success of chip design. Today, chips are more complex than ever and this causes them to exhibit unexpected behaviors that could be fatal for their productization in the market. Specifically, we are interested in verification of MPSoCs in one hand and asynchronous circuits on the other. The microelectronic industry is using logic simulation and formal or semi-formal methods to perform verification.

In DSD lab we do research in different areas to reach the bellow goals, leading to the design of dependable systems, used in embedded systems for certain class of applications. We also look into design of specific CAD tools which will facilitate our approach.

Goals & Objectives

Identifying undesirable factors and their effects on the functionality of digital systems.

Proposing methods to eliminate these factors in order to establish the main features of a dependable system which are availability, reliability and integrity.

Implementing CAD tools which allow the high level specification and design of dependable and energy-efficient VLSI systems by using asynchronous techniques.

Synthesis of low latency and low power design. Proposing algorithms and digital circuitries to achieve low power, high speed and dependable integrated circuits.

Design of on-chip communication links using special encoding to achieve better power-reliability-performance and noise robustness.

Ensuring that what we mean to design corresponds to the chip's actual behavior. This can be done through Functional and Formal Verification.

(2016) - Left-to-right: Sina, Ana, Saba, Taghi, Meisam, Dr. Mohammadi, and Alireza.
(2017) - Left-to-right: Mohammad Hossein, Sina, Meisam, Dr. Mohammadi, Mohammad, Saba, Kawsar, Taghi, Alireza, and Farzad.

Latest Publications

A high performance dual clock elastic FIFO network interface for GALS NoC

Seyed Mohamad Taghi Adl, Siamak Mohammadi

| 2018

Elastic buffer evaluation for link pipelining under process variation

Seyed Mohamad Taghi Adl, Mohammad Mirzaei, Siamak Mohammadi

| 2018

A Majority-Based Reliability-Aware Task Mapping in High-Performance Homogenous NoC Architectures

Alireza Namazi, Meisam Abdollahi, Saeed Safari, Siamak Mohammadi

| 2018

Exploration of approximate multipliers design space using carry propagation free compressors

Sina Boroumand, Hadi P Afshar, Philip Brisk, Siamak Mohammadi

| 2018

CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design

Sina Boroumand, Hadi P Afshar, Philip Brisk, Siamak Mohammadi

| 2017

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We got new theme for our DSD lab website.


Congratulations to Sina Boroumand and Saba Jamilan who defended their MSc. thesis.


It is launched! Announcing the launch of DSD lab newly redesigned website

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Current Projects

Contact Us

Dr. Siamak Mohammadi

Dependable System Design Laboratory (Room No. 221)

University of Tehran

School of Electrical and Computer Engineering

North Kargar Ave

Tehran, Iran

PO Box: 14395/515

Phone: +98 21 61114306

smohamadi [at] ut [dot] ac [dot] ir