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Sina Boroumand

Msc. Graduate

Tehran, Iran

sina.boroumand [at] gmail.com

sinaxs


Skills

Hardware Languages

VHDL, Verilog, System Verilog, HSPICE

Programming Languages

C/C++, C#, PHP, Python, Bash, MATLAB, Assembly, VBA, Java, Qt

Web Development

HTML5, CSS3, MySQL, JavaScript, Ajax, JQuery

Tools and Simulators

ModelSim, Altera Quartus, Xilinx ISE, VTR, SimpleScalar, MARSS, Booksim, Graphite, Balsa, Petrify, ABC

Miscellaneous

Keil ARM, Codevision AVR, Proteus
UNIX, Linux, LaTex, MS Office, Adobe Photoshop

Languages

Persian (Native)
English
French

Hobbies

Playing Musical Instruments (Piano and Guitar)
Photography
Video Games
Soccer



Sina Boroumand

Hi, I'm Sina, a computer engineer and MSc. student of Computer Engineering majoring Computer Architecture in the University of Tehran currently living in the city of Tehran, Iran.

I am a member of the Dependable System Design (DSD) Lab, under supervision of Dr. Siamak Mohammadi. We are mainly researching on design of fault-tolerant and reliable VLSI systems.

My major research interest is reconfigurable architectures, approximate circuit design and low-power embedded systems. I am currently working on my master's thesis which is about exploring design space of approximate arithmetic units like adders and multipliers. My skill sets span over both hardware design techniques (using HDLs) and software programming (C/C++). Right now, I am looking for a position to continue my education in PhD. Here is my CV.

Research Interest

- Approximate Circuit Design

- Reconfigurable Computing

- Computer Arithmetic

- Computer Architecture

- Low Power Multicore Embedded Systems

6 Nov 2017

Our paper "Approximate Quadruple Addition with the Fast Carry Chains of FPGAs" has been accepted in Design, Automation & Test in Europe Conference & Exhibition (DATE) 2018.

24 Sep 2017

Submitted a paper "Approxiate Adder Tree Synthesis for FPGAs" to 26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) 2018.

19 Sep 2017

Submitted a paper "Approximate Quadruple Addition with the Fast Carry Chains of FPGAs" to Design, Automation & Test in Europe Conference & Exhibition (DATE) 2018.

11 Sep 2017

Our paper "Exploration of Approximate Multipliers Design Space using Carry Propagation Free Compressors" has been accepted for presentation in ASP-DAC conference located in Jeju Island, South Korea.

22 Jul 2017

Our paper "CAL: Exploring Cost, Accuracy, and Latency in Approximate and Speculative Adder Design" has been accepted for presentation in DFT conference located in Cambridge, UK.

18 Jul 2017

Submitted "Exploration of Approximate Multipliers Design Space using Carry Propagation Free Compressors" to ASP-DAC conference located in Jeju Island, South Korea.